Patent Document 1 discloses circuit elements for formulating a semiconductor integrated circuit by modeling a semiconductor substrate in terms of resistance element(s), inductance element(s), and capacitance element(s), and a technology for performing operation characteristic analysis using a circuit simulator. In Patent Document 1, when a configuration of a large number of very small substrate contacts is modeled and the number of nodes in the model becomes very large, modeling of a smaller substrate contact structure by modeling a local voltage drop produced by a current concentration in a vicinity of the substrate contacts using a hemispheric resistor is proposed from a viewpoint that simulation becomes very long.
Patent Document 2 discloses an analysis method for substrate noise characterized by having a step of applying a static timing analysis (STA) algorithm to a description of a digital circuit, and generating timing information related to 1 or more gates in the digital circuit; a step of applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information related to 1 or more gates in the digital circuit, and a description of a switching operation of the digital circuit to generate a current waveform; and a step of generating a reduced model (RM) for simulation of the digital circuit, according to a model of a package of the description of the digital circuit, the current waveform, and the digital circuit, and, by RM simulation of the digital circuit, generating an index of substrate noise related to the digital circuit.
Patent Document 3 discloses a method of determining a diffusion resistance calculation formula for an impurity diffusion layer when designing an LSI circuit.
In addition, Non-Patent Document 1 discloses a method of high accuracy simulation of substrate noise affecting performance of an analog circuit disposed inside the same substrate, by generating a macro-model with primitive instance units. Here, the term “(primitive) instance” indicates a name for uniquely identifying a cell indicating a logical unit in the substrate.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P2002-158284A    [Patent Document 2]    JP Patent Kokai Publication No. JP-P2006-236340A    [Patent Document 3]    JP Patent Kokai Publication No. JP-A-9-128433    [Non-Patent Document 1]    Marc van Heijningen et al., “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, 2000 DAC, FIG. 1.